1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device that can stop generating an internal voltage.
2. Description of Related Art
In many semiconductor devices, an internal voltage is generated inside thereof based on an external voltage. The internal voltage is used to operate some circuit blocks. Even in this case, a circuit block that serves as an interface to outside needs to operate on the external voltage. As a result, a signal of a circuit that operates on the internal voltage is different in amplitude from a signal of a circuit block that operates on the external voltage. Therefore, a level shifter is inserted between the circuit blocks to convert the amplitude of the signals. In Japanese Patent Application Laid-Open No. 2004-153689 discloses a level shifter that includes a flip-flop latch circuit of a current mirror type and a CMOS inverter circuit.
Meanwhile, a DRAM (Dynamic Random Access Memory), which is one of typical semiconductor devices, has an operation mode called a deep power down mode (See Japanese Patent Application Laid-Open No. 2012-38389). The deep power down mode is an operation mode to minimize power consumption, as well as to maintain a standby state, by stopping operations of most of circuits in the DRAM. Once the DRAM enters the deep power down mode, the generation of internal voltage is also stopped, thereby stopping most of circuit blocks that are designed to operate on the internal voltage. However, even when the DRAM enters the deep power down mode, some circuit blocks that serve as an interface to the outside remain activated. The circuit blocks that serve as an interface to the outside are designed to operate on the external voltage. Therefore, for example, a level shifter disclosed in Japanese Patent Application Laid-Open No. 2004-153689 needs to be inserted between the circuit blocks operating on the external voltage and the circuit blocks operating on the internal voltage.
The present inventor has made extensive studies to improve a semiconductor device having an operation mode in which the generation of internal voltage is stopped as in the case of the deep power down mode.